This degree project (EELE-2910-WA) demonstrates the complete design and implementation of a 4-bit Arithmetic Logic Unit (ALU) on an Altera DE10-Lite FPGA development board featuring the MAX 10 10M50DAF484C7G device. The ALU performs four distinct operations with results displayed on dual 7-segment displays.

Developed as part of Digital VLSI Circuit Design coursework at Lakehead University, this project showcases practical FPGA programming, Verilog HDL implementation, and comprehensive verification through ModelSim RTL simulation and physical hardware testing.

• XNOR Logic Operation: Bit-by-bit XNOR operation between 4-bit inputs A and B with cascaded gate implementation
• Shift-Left Operation: Single-bit left shift of input A with MSB overflow detection and zero insertion
• 4-Bit Addition: Full adder implementation with ripple carry propagation and overflow flag generation
• 4-Bit Multiplication: Partial product generation using shift-and-add algorithm with 8-bit result output
• Dual Display Output: Two 7-segment displays showing upper and lower nibbles of 8-bit results

• Altera DE10-Lite Board: Intel MAX 10 FPGA with 50,000 logic elements and 1,677 LABs
• Input Interface: 10 slide switches (SW9-SW0) for 4-bit operands A, B and 2-bit operation select
• Output Display: HEX1 and HEX0 seven-segment displays for result visualization
• Clock Distribution: 50 MHz system clock with proper timing constraints
• Resource Utilization: Efficient logic synthesis with minimal LUT and register usage

• Top-Level Module: Complete ALU module with input/output declarations and operation multiplexer
• Operation Modules: Separate Verilog modules for each ALU function ensuring modularity and reusability
• Seven-Segment Decoder: Binary-to-7-segment conversion module for hexadecimal display output
• Combinational Logic: Purely combinational design with instant result computation
• Hierarchical Design: Structured module hierarchy with clear signal flow and documentation

• ModelSim RTL Simulation: Comprehensive testbench validation with all input combinations
• Waveform Analysis: Signal timing verification ensuring correct operation propagation
• Hardware Testing: Physical FPGA testing with all switch combinations and display verification
• Truth Table Validation: Complete verification against theoretical operation truth tables
• Performance Analysis: Timing analysis ensuring meeting FPGA clock constraints

• Quartus Prime Integration: Complete project setup with pin assignments and constraints
• Logic Synthesis: Automatic optimization for MAX 10 architecture with resource reporting
• Pin Assignment: Systematic mapping of switches to FPGA pins (PIN_C10 through PIN_A8)
• Display Connections: 7-segment display pin mapping for HEX0 and HEX1 outputs
• Programming & Download: Successful FPGA configuration and real-time operation validation

• Successful Implementation: All four ALU operations working correctly on physical hardware
• Display Functionality: Clear hexadecimal output on both 7-segment displays
• Simulation Verification: 100% pass rate on ModelSim RTL simulation testing
• Resource Efficiency: Optimized logic utilization within FPGA constraints
• Educational Impact: Comprehensive understanding of FPGA design flow and HDL programming

• Hardware: Altera DE10-Lite FPGA board with Intel MAX 10 10M50DAF484C7G device
• Programming: Verilog HDL for all module implementations and testbenches
• Development Tools: Intel Quartus Prime for synthesis, place & route, and FPGA programming
• Simulation: ModelSim RTL simulator for comprehensive design verification
• Design Flow: Complete FPGA development cycle from HDL to hardware implementation
• Testing: Physical hardware validation with switch inputs and 7-segment display outputs